1. Field of the Art
This invention relates to an error correction coding and decoding circuit for digitally coded character information or graphic information, etc., and more particularly, to the configuration of an error correcting circuit for codes which can be decoded by hard logic, i.e., majority-logic elements.
2. Prior Art
In the prior art, as shown in Japanese Patent Application Laid-Open Nos. 133751/84, 181841/84 and 216388/84, most error correcting coding and decoding circuits of this kind become operative after initialization by program through the CPU. In this instance, a single clock signal is used and therefore the delay in the error correcting circuit is large. For serial data, a system was adopted to use two or more error correcting circuits of the same construction, to load data alternately.
In addition, the encoding circuit has no control signal to and from an external circuit, making such a circuit difficult to use as regards timing, etc.
Conventional error correction decoding circuits have a system to connect to a CPU to set initial and other conditions by program. Thus, they were difficult to use in a circuit comprised of only hard logic elements without a CPU.